DESIGN OF LOW POWER 4-BIT FULL ADDER USING SLEEPY KEEPER APPROACH

Low Power Optimization Of Full Adder, 4-Bit Adder And 4-Bit BCD Adder

Micro-electronic devices are playing a very prominent role in electronic equipments which are used in daily life. For electronic equipment battery life is important. So, in order to reduce the power consumption we implement a Sleepy technique to the electronic circuits. Sleepy technique is also called as power gating technique. In the power gating structure, a circuit operates in two different ...

Technical Report GIT-CERCS-06-03 The Sleepy Keeper Approach: Methodology, Layout and Power Results for a 4-bit Adder

Ultra Low Power 1-Bit Full Adder

In this paper we propose a new 9 transistor 1-bit full adder. The proposed circuit performs efficiently in subthreshold region to employ in ultra low power applications. The main design objective for this new circuit is low power consumption and full voltage swing at a low supply voltage. The proposed cell also remarkably improves the power consumption, power delay product and has better noise ...

Sleepy Keeper Approach for Power Performance Tuning in VLSI Design

There are several techniques that reduce leakage power in efficient way but the disadvantage of each technique limits the application of each technique. In this paper sleepy keeper approach is introduced to reduce the power dissipation of the circuit in idle state when its logic is not needed. The sleepy keeper approach uses traditional sleep transistors and two additional transistors which are...

Low Leakage Multi Threshold Level Shifter Design using Sleepy Keeper

In this paper, a low leakage multi Vth level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. Multi Threshold CMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Power dissipation has become an overriding concern fo...